
`include "common_header.verilog"

//  *************************************************************************
//  File : rg_40g.vhd
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2008 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Denis Poverennyy
//  info@morethanip.com
//  *************************************************************************
//  Description : The register block is FF based storage to keep data from the
//  deskew buffer
//  Version     : $Id: rg_40g.v,v 1.4 2014/10/20 08:07:41 dk Exp $
//  *************************************************************************

module rg_40g (
   reset_rxclk,
   cgmii_rxclk,
   sw_reset,
   desk_buf_0_data,
   desk_buf_1_data,
   desk_buf_2_data,
   desk_buf_3_data,
   desk_buf_data_val,
   desk_buf_0_data_r,
   desk_buf_1_data_r,
   desk_buf_2_data_r,
   desk_buf_3_data_r);

parameter rg_width = 66;

input   reset_rxclk;                            //  async active high reset
input   cgmii_rxclk;                            //  cgmii clock
input   [3:0]            sw_reset;              //  software reset

input   [rg_width - 1:0] desk_buf_0_data;       //  buffer 0 data
input   [rg_width - 1:0] desk_buf_1_data;       //  buffer 1 data
input   [rg_width - 1:0] desk_buf_2_data;       //  buffer 2 data
input   [rg_width - 1:0] desk_buf_3_data;       //  buffer 3 data
input   [3:0]            desk_buf_data_val;     //  data valid
output  [rg_width - 1:0] desk_buf_0_data_r;     //  buffer 0 data
output  [rg_width - 1:0] desk_buf_1_data_r;     //  buffer 1 data
output  [rg_width - 1:0] desk_buf_2_data_r;     //  buffer 2 data
output  [rg_width - 1:0] desk_buf_3_data_r;     //  buffer 3 data 

reg     [rg_width - 1:0] desk_buf_0_data_r; 
reg     [rg_width - 1:0] desk_buf_1_data_r; 
reg     [rg_width - 1:0] desk_buf_2_data_r; 
reg     [rg_width - 1:0] desk_buf_3_data_r; 



always @(posedge cgmii_rxclk or posedge reset_rxclk)
   begin 
   if (reset_rxclk == 1'b 1)
      begin
      desk_buf_0_data_r <= {(rg_width){1'b 0}};	
      desk_buf_1_data_r <= {(rg_width){1'b 0}};	
      desk_buf_2_data_r <= {(rg_width){1'b 0}};	
      desk_buf_3_data_r <= {(rg_width){1'b 0}};	
      end
   else
      begin

      if (sw_reset[0] == 1'b 1)
         begin
         desk_buf_0_data_r <= {(rg_width){1'b 0}};	
         end
      else if (desk_buf_data_val[0] == 1'b 1)
         begin
         desk_buf_0_data_r <= desk_buf_0_data;	
        end
        
        
      if (sw_reset[1] == 1'b 1)
         begin
         desk_buf_1_data_r <= {(rg_width){1'b 0}};	
         end        
      else if (desk_buf_data_val[1] == 1'b 1)
         begin
         desk_buf_1_data_r <= desk_buf_1_data;	
         end

      if (sw_reset[2] == 1'b 1)
         begin
         desk_buf_2_data_r <= {(rg_width){1'b 0}};	
         end
      else if (desk_buf_data_val[2] == 1'b 1)
         begin
         desk_buf_2_data_r <= desk_buf_2_data;	
         end

      if (sw_reset[3] == 1'b 1)
         begin
         desk_buf_3_data_r <= {(rg_width){1'b 0}};	
         end
      else if (desk_buf_data_val[3] == 1'b 1)
         begin
         desk_buf_3_data_r <= desk_buf_3_data;	
         end

      end
   end


endmodule // module rg_40g

